Packaging of chips may prevent degradation of the electrical performance of chip circuits caused by impurities in the air. Moreover, the packaged chips are also convenient for transportation and installation. The packaging quality may directly affect the performance of the chip and also affect the design and the manufacturing of the printed circuit board connected to the chip.
The current packaging technology has been gradually transitioned from surface-mounting technology and ball grid array (BGA) terminal package technology to three-dimensional (3D) packaging technology. The 3D packaging technology may be categorized into different types, such as package-stacked-type 3D packaging technology, chip-stacked-type 3D packaging technology, wafer-stacked-type 3D packaging technology, etc. The 3D packaging technology demonstrates a number of advantages including the ability to improve the density of interconnections and the ability to reduce the overall height of the final device.
However, there is still a need to improve the packaging technology to provide desirable wafer-bonding to meet requirements of the development in semiconductor technology. The disclosed wafer bonding methods and wafer-bonded structures are directed to solve one or more problems set forth above and other problems in the art.